The cellular phone industry continues to thrive by providing support for Bluetooth personal area networking, positioning technology based on GPS and wireless LAN for high-speed local-area data access. Sophisticated applications, such as MP3 audio playback, camera functions, MPEG video and digital TV further entice a new wave of handset replacements. Such application support dictates a high level of memory integration together with large digital signal processing horsepower and information flow management, all requiring sophisticated DSP and microprocessor cores. To keep cost and power dissipation down, as well as to constrain growth of printed circuit board (PCB) real estate, the entire radio, including memory, application processor (AP), digital baseband (DBB) processor, analog baseband and RF circuits would ideally be all integrated onto a single silicon die with a minimal number of external components.
Currently, the DBB and AP designs invariably migrate to the most advanced deep-submicron digital CMOS process available, which usually does not offer any analog extensions and has very limited voltage headroom. Design flow and circuit techniques of contemporary transceivers for multi-GHz cellular applications are typically analog intensive and utilize process technologies that are incompatible with DBB and AP processors. The use of low-voltage deep-submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits. Furthermore, any mask adders for RF/analog circuits are not acceptable from fabrication cost standpoint. Consequently, a strong incentive has arisen to find digital architectural solutions to the RF functions. One approach to reduce the cost, area and power consumption of the complete mobile handset solutions is through integration of the conventional RF functions with the DBB and AP.
Quadrature amplitude modulation (QAM) is a modulation technique in widespread use today. A block diagram illustrating a prior art Cartesian architecture QAM modulator with I and Q baseband signals is shown in FIG. 1. The modulator, generally referenced 10, comprises a coder 12, I and Q TX pulse-shaping filters 14, 16, cos and sin multipliers of a local oscillator clock 18, 20 and adder/summing node 22. In operation, the input bit stream bk is converted by the coder to I (real) and Q (imaginary) symbols. These are pulse-shaped and the resulting baseband signals are multiplied by the cos and sin clock signals of the local oscillator to generate in-phase and quadrature phase components, respectively. These are combined to generate the output RF signal x(t). Note that this Cartesian modulation scheme could be implemented digitally, which is desirable considering the benefits of digital implementation of circuitry typically implemented in analog.
Complex modulation may also be generated using a polar modulation scheme to substitute for the quadrature modulation of FIG. 1. A circuit diagram illustrating prior art polar complex modulation based on direct phase and amplitude modulation is shown in FIG. 2. The circuit, generally referenced 30, comprises a coder 32, I and Q TX filters 34, 36, polar coordinate converter 38, local oscillator 40 and multiplier 42.
In operation, the bits bk to be transmitted are input to the coder, which functions to generate I (real) and Q (imaginary) symbols therefrom according to the targeted communications standard. The I and Q symbols are pulse-shaped and the resulting baseband signals are converted to phase (Ang{s(t)}), and magnitude (Mag{s(t)}) baseband signals by the polar coordinate converter 38. The phase data is used to control the local oscillator 40 to generate the appropriate frequency signal, which is multiplied in multiplier/mixer 42 by the magnitude data resulting in the output RF signal x(t). Note that this polar modulation scheme is better suited for digital implementation.
Considering an all-digital implementation, the local oscillator 40 can be made extremely accurate. By nature, the polar architecture natively operates in the frequency domain where the frequency is the derivative of the phase with respect to time. Depending on the type of modulation implemented, the change in frequency Δf from one command cycle to another can be very large for sudden phase reversals that occur near the origin in the I/Q domain representing the complex envelope. Considering a WCDMA system, for example, a plot of Δf versus time is shown in FIG. 3A. Most of the time, the frequency deviation is reasonably small. The dashed lines represent the threshold point whereby the frequency deviation Δf is outside of the dashed lines approximately 0.3% of the time. The polar modulator cannot easily handle such large swings in Δf due to the inherent construction of the polar modulator, which is a limitation of the polar structure addressed by the present invention.
The conventional Cartesian modulator, on the other hand, operates natively in the phase domain and avoids handling the large swings in frequency. A disadvantage of this scheme, however, is in its difficulty to achieve high resolution compared to the polar scheme. Additionally, amplitude and phase mismatches of the I and Q paths result in the modulation distortion.
The polar modulation scheme, however, lends itself well to implementation using deep submicron CMOS technology. A problem arises when this scheme is applied to WCDMA applications which generate frequency deviations Δf that are too large for the polar modulator to handle.
Thus, there is a need for a modulator structure that (1) combines the advantageous features of both the Cartesian and polar schemes, (2) avoids the disadvantages of both Cartesian and polar modulators, (3) is well suited for implementation in deep submicron CMOS processes, and (4) is able to handle the large Δf swings generated in WCDMA and other advanced modulation schemes.